Multiple function type D/A converter

ABSTRACT

A multiple function type D/A converter utilizing a ladder type resistance circuit, and capable of other mathematical functions in addition to the D/A conversion, having a series resistance circuit consisting of N number of resistors R2 1  ˜R2 n  each having a resistance value R connected in series between an output terminal V o  and one side of a terminal resistor R o  which has a resistance value 2R and is connected on its other side to ground, such series circuit including a resistor connecting point between each adjacent pair of resistors R 0 , R2 1  ˜R2 N , and branching in parallel therefrom N+1 number of groups of parallel resistors 01˜0n, 11˜1n, . . . N1˜Nn, each containing n resistors where n is an integer greater than 1, the n resistors of each such group being all connected on one side to the same resistor connecting point with different groups thereof connected to different connecting points along such series circuit, the n resistors of each such group being individually switchable on the other side thereof alternately between ground and a reference voltage V s  by means of corresponding groups of switching circuits S 01  ˜S 0n  . . . S N1  ˜S Nn  under the control of applied digital signals.

FIELD OF THE INVENTION

The present invention relates to a multi-function type D/A converterusing a resistance circuit and which is capable of executing a varietyof mathematical functions while converting an input digital signal,based on the natural binary code, into an analog signal having a voltagelevel corresponding to such digital value.

BACKGROUND OF THE INVENTION

FIG. 8 shows a typical known circuit of this type for D/A conversion,consisting of a so-called "R-2R ladder" type circuit or network whereina set of resistors R1₀ ˜R1_(N) each having a resistance value of 2Requal in number to the number N plus 1 (N+1) are each connected inparallel with a terminating resistor R₀ which has a resistance value 2Rand is connected to ground along a series of series resistors R2₁˜R2_(N) having a resistance value R, and ending in an output terminalV₀, the individual parallel resistors being connected by switchingcircuits S₀ ˜S_(N) alternately between a source of reference voltageV_(s) and ground, such switching circuits being controlled by digitalsignals b₀ ˜b_(N). As is obvious, when the digital signals b₀ ˜b_(N) ofeach digit become high ("On"), the reference voltage V_(s) is applied tothe corresponding parallel resistors R1₀ ˜R1_(N). Accordingly, an analogoutput voltage V₀ is generated at the output terminal according to thefollowing equation (1) :

    V.sub.0 =(V.sub.s /2)×(b.sub.0 ·2.sup.-N +b.sub.1 ·2.sup.-(N-1) + . . . +b.sub.N-1 ·2.sup.-1 +b.sub.N ·2.sup.0)                                        (1)

Where, b₀ ˜b_(N) are 1 or 0, either high or low. The value of V₀ islowered from the value indicated by the equation (1) when a terminatingresistor or adjusting resistor is connected to the output terminal dueto the resistance thereof.

Thus, the ladder type D/A converter operates as a D/A converter throughthe switching between ON and OFF of the parallel resistors R1₀ ˜R1_(N)in accordance with the digital signals and therefore if a circuitcapable of carrying out other mathematical functions required, e.g.,such as addition and subtraction before or after the conversion, suchcircuit must be provided in addition to the D/A converter circuit.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a multipleoperation type D/A converter utilizing a ladder type resistance circuitwhich is capable of other mathematical functions in addition to the D/Aconversion.

In order to attain such object, the present invention uses a circuitarranged as shown in FIG. 1, wherein a series resistance circuitconsisting of N number of resistors R2₁ ˜R2_(n) each having a resistancevalue R is connected between an output terminal V_(o) and one side of aterminal resistor R_(o) which has a resistance value 2R and is connectedon its other side to ground, such series circuit including a resistorconnecting point between each pair of resistors R_(o), R2₁ ˜R2_(N) hasbranching in parallel therefrom N+1 number of groups of parallelresistors 01˜0n, 11˜1n, . . . N1˜Nn, each group containing n resistorswhere n is an integer greater than 1, the n resistors of each such groupbeing all connected on one side to the same resistor connecting pointwith different groups of resistors connected to different connectingpoints along such series circuit, the n resistors of each such groupbeing individually connected on the other side alternately betweenground and a reference voltage V_(s) by means of corresponding groups ofswitching circuits S₀₁ ˜S_(0n) . . . S_(N1) ˜S_(Nn) under the control ofapplied digital signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a general circuit diagram of a multiple function type D/Aconverter of the present invention. The connection of the respectiveswitching contacts to the source of reference voltage V_(s) beingomitted.

FIG. 2 to FIG. 5 show circuit diagrams illustrating the principles forcarrying out functions other than the D/A conversion by utilizing theladder type D/A converter circuit shown in FIG. 1.

FIG. 6 and FIG. 7 show circuit diagrams of other embodiments of thepresent invention.

FIG. 8 shows a conventional ladder type D/A converter circuit of theprior art.

DETAILED DESCRIPTION OF THE INVENTION

When the circuit of this invention is operated as an ordinary D/Aconverter, the switch circuits S₀₁ ˜S_(0n). . . S_(N1) ˜S_(Nn) arerespectively controlled by the common digital signal for each group orpartly controlled by that signal (for example, the first switch of eachgroup S₀₁ ˜S_(N1)) with the remaining switching circuits of each group(S₀₂ ˜S_(0n) . . . S_(N2) ˜S_(Nn)) being otherwise controlled to connectall but one of the parallel n resistors of each group to the referencepotential V_(s) by setting the control signal for the latter at theirlow level ("OFF"). Thus, the total resistance value of each group of nresistors R1₀₁ R1_(0n), . . . R1_(N1) ˜R1_(Nn) becomes 2R and isconnected to the reference voltage V_(s) and therefore the circuitstructure becomes equivalent to FIG. 8 and performs D/A conversion inaccordance with equation (1). As other switching circuits of each ngroup are activated to bring additional n resistors (of resistance value2nR) into the circuit with reference voltage V_(s), the voltage ofreference voltage source is correspondingly lowered in proportion to thenumber of such resistors, having resistance value 2nR, connected at thesame time to the reference potential for each group. Thus, the D/Aconversion is carried out and gives a correspondly lowered output signalvoltage. For example, when only one switch circuit S₀₁ ˜S_(N1) iscontrolled in each digit, the circuit becomes equivalent to that shownin FIG. 2 and an output signal V₀ is expressed as indicated in equation(2) below, in place of the equation (1).

    V.sub.0 =(V.sub.s /2n)(b.sub.0 ·2.sup.-N +b.sub.1 ·2.sup.-(N-1) + . . . +b.sub.N ·2.sup.0)(2)

If the circuit is to be operated as an adder, the resistors R1₀ ˜R1_(N)of each digit are activated according to the number of adding signals nand the associated switch circuits S₀₁ ˜S_(0n), . . . S_(N1) ˜S_(Nn) arecontrolled by the associated digital signals b₀₁ ˜b_(0n), b_(N1) ˜b_(Nn)to be added. Thereby, the digital signals to be added are converted toanalog signals and outputed additively to the output terminal.

When the circuit is to be operated as a subtracter, the resistors R1₀˜R1_(N) of each digit group are composed of the resistors in such numberas the input signals and the digital signals of switches S₀ ˜S_(N)corresponding to the signal to be subtracted or minus signal aresupplied through inverters. Thereby, subtraction processing for theinput signal not inverted is carried out. FIG. 3 is an example of acircuit for subtracting a second input signal from a first input signal.The inverters A₀ ˜A_(N) are interposed in the control lines of switchcircuits S₀₂ ˜S_(N2) for the second signal. Thereby, when both inputsignal values coincide, namely, when the result of subtraction is zero,the one is inverted and the added digital values all become "high".Accordingly, the output signal V₀ is generated so that the referencevoltage V_(s) is applied respectively to the one of the parallelresistor pairs R1₀₁, R1₀₂, R1₁₁, R1₁₂ ; . . . ; R1_(NL), R1_(N2) of eachdigit group. Thus, the output V₀ is expressed as follows from theequation (2).

    V.sub.0 =(V.sub.s /4)(b.sub.0 ·2.sup.-N +b.sub.1 ·2.sup.-(N-1) + . . . +b.sub.N ·2.sup.0)(3)

Therefore, the voltage of output signal V₀ increases or decreases inaccordance with the result of subtraction, even shifting the polarity(+, -) with reference to the voltage, as defined by the equation (3)which applies when the result of subtraction is zero.

Where the circuit is to be operated as a coincidence detection circuitfor two digital signals, detection occurs in the same way that theoutput signal V₀ is generated or not when values of b₀ ˜b_(N) ofequation (3) are all "high" in FIG. 3.

For the circuit to be operated for compensating voltage, two resistorsin each digit group are used as the parallel resistors R1₀ ˜R1_(N) asshown in FIG. 4, e.g., R1₀₁ ˜R1_(N1) and R1₀₂ ˜R1_(N2), and these groupsof resistors, i.e., the "1" group and the "2" group are connected todifferent reference voltage sources set to the voltage of equal butopposite polarity such as +V_(s) and -V_(s). Thereby, the output signalV₀ becomes the compensation voltage for the reference voltage and whenthe reference signal coincides with the input signal, the output voltageV₀ becomes zero. The circuit is thus operated as the subtractor whichgenerates a negative voltage for a negative subtraction result.Moreover, as shown in FIG. 5, it is also possible to connect the outputterminal of the subtraction circuit of FIG. 3 to a succeeding stageutilizing an operational amplifier A_(op) having a reference level whichis equal to the voltage obtained when values of b₀ ˜b_(N) of equation(3) are all set to "1". When the input signal coincides with thereference signal, an output of the operational amplifier A_(op) becomeszero.

FIG. 6 shows a 3-bit 2-input type multiple-function type D/A converter,wherein the reference voltage V_(s), common to all inputs, is set to +10V and a variable resistor RV1 for adjusting output voltage is connectedto the output terminal.

If the converter of FIG. 6 is operated as in the addition mode, anoutput signal V₀ is obtained at the output terminal according toequation (3), but modified by a coefficient K (1˜0) preset by thevariable resistor RV1, by respectively controlling the switch circuitsS₀₁ ˜S₂₁ and S₀₂ ˜S₂₂, with two digital signals b₀₁ ˜b₂₁ and b₀₂ ˜b₂₂,the modified equation being as follows :

    V.sub.0 =K(5/2)(b.sub.01 +b.sub.02)·2.sup.-2 +(b.sub.11 +b.sub.12)·2.sup.-1 +(b.sub.21 +b.sub.22)·2.sup.0(4)

Thus, when both digital signals are "high" the maximum output voltage V₀is equal to K×(35/4) volts.

For the circuit to be operated in the concidence mode or subtractionmode, one set of digital signals b₀₂, b₁₂, b₂₂ are respectively suppliedto the switch circuits S₀₂ ˜S₂₂ through inverters similar to those shownin FIG. 4. Accordingly, when both sets of digital signals coincide, anoutput signal V₀ =K×(35/8) volts is generated from the equation (4) asexplained above. Thereby, not only is coincidence detected but also anydifference between the output signal V₀ and the reference voltage isobtained as a result of analogous subtraction.

When the circuit is operated as a compensating circuit, as shown in FIG.7, an operational amplifier A_(op1) generates a voltage difference ΔVbetween the reference voltage K(35/8) obtained from the equation (4)mentioned above and the output signal V₀ shown in FIG. 6. Therefore, thecircuit is so controlled that the reference signal coincides with theinput signal, making zero the voltage difference ΔV through the feedbackof voltage difference ΔV to the control circuit 10.

According to the multiple function or mode type D/A converter of thepresent invention, the parallel resistors of the conventional laddertype resistance circuit are each composed of several resistors, and thismodified circuit can be operated to simultaneously carry out a D/Aconversion as well as any of a variety of other functions, such asaddition, subtraction, compensation, balance or coincidence detection,etc., by controlling the respective resistors to the "low" or "high"levels with the digital signals. Further, additional stages of thecircuit can be provided more simply and economically than by addingentire extra circuits for these respective functions.

Particularly, when used for coincidence detection, this circuit onlyrequires accurately fixing the values of the resistance elementsarranged face to face and accuracy will be remarkably improved ascompared with the use of a plurality of ordinary ladder type D/Aconverters for this purpose.

What is claimed is:
 1. A multiple function type D/A converter comprisinga terminating resistor having a resistance value 2R of which oneterminal is connected to ground; a series resistance circuit consistingof a plurality of resistors equal in number to N, each having aresistance value R, connected in series between an output voltageterminal and the other terminal of said terminating resistor, saidseries circuit including N+1 number of resistor connecting pointsbetween each adjacent pair of N resistors and the terminating resistorand the adjacent N resistor; branching in parallel from said seriescircuit N+1 number of groups of n number of parallel resistors, eachhaving a resistance value 2nR, the n resistors of each such group beingall connected on one side to the same resistor connecting point withdifferent groups thereof connected to different connecting points alongsuch series circuit, the n resistors of each such group beingindividually switchable on the other side alternately between ground anda reference voltage by means of corresponding groups of switchingcircuits under the control of applied digital signals, N and n eachbeing an integer at least equal to 2.